Rethinking DRAM design and organization for energy-constrained multi-cores

TLDR

DRAM vendors have prioritized cost‑per‑bit, leading to energy‑inefficient features such as overfetch, while modern servers face high operating costs, queuing delays, reliability energy demands, and limited locality from multi‑core workloads. The authors argue that these trends require a redesign of DRAM architecture, even at the expense of a modest increase in cost‑per‑bit.

Abstract

DRAM vendors have traditionally optimized the cost-per-bit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, where a single request activates thousands of bit-lines in many DRAM chips, only to return a single cache line to the CPU. The focus on cost-per-bit is questionable in modern-day servers where operating costs can easily exceed the purchase cost. Modern technology trends are also placing very different demands on the memory system: (i)queuing delays are a significant component of memory access time, (ii) there is a high energy premium for the level of reliability expected for business-critical computing, and (iii) the memory access stream emerging from multi-core systems exhibits limited locality. All of these trends necessitate an overhaul of DRAM architecture, even if it means a slight compromise in the cost-per-bit metric.