Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

Abstract

We present, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">for</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">the</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">first</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">time</i> , the monolithic integration of Gate-Ail-Around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. The drive currents for N-and P-MOS transistors are matched using different number of channels for each to obtain symmetric pull-up and pull-down characteristics. Sharp ON-OFF transitions with high voltage gains (up to -45) are obtained which are best reported among the nanowire and carbon nanotube inverters. The inverters maintain their good transfer characteristics and noise margins for a wide range of VDD values, down to 0.2 V. Short circuit current at 0.2 V VDD is ~6 pA indicating excellent potential of these devices for low voltage and ultra low power applications. These results excel those reported in the literature for nanowire as well as FinFET (non-classical CMOS) inverters.