Linearity, noise optimization for two stage RF CMOS LNA

Abstract

Deep sub-micron CMOS technology is a good candidate for a wireless communication RF IC because of the integration possibility of IF and RF modules together. For optimum noise performance, the CMOS transistor layout and bias condition are analyzed and discussed. In this paper along with the noise optimum condition, a linearity improvement technique for a cascaded LNA is presented. The LNA for mobile applications should satisfy the noise, linearity and gain performance under the current consumption constraint. If an LNA is designed with more than a two stage structure, then the first stage MOS ought to be optimized for low noise performance in terms of the bias condition and its size because the first stage MOS is the dominant noise contributor of all the cascade stage. The last stage is constructed for linearity optimization, because the last stage linearity is influential for a cascaded LNA.