An asynchronous pipelined lattice structure filter

Abstract

We derive an asynchronous, delay-insensitive CMOS circuit to implement a finite impulse response lattice structure filter. Simulation indicates a performance in the range of 380 million multiplications and 980 million additions per second in Hewlett-Packard's 0.8 /spl mu/m technology (/spl lambda/=0.5 /spl mu/m). We obtain high throughput by using deep pipelines and buffering the carry chains of adders and multipliers. Our work demonstrates that formal design can easily yield circuits which are safe and fast.