Latch-up immunity against noise pulses in a CMOS double well structure

Abstract

Latch-up immunity in a CMOS double well structure against a pulsive noise when the noise is applied to the p-well has been studied both theoretically and experimentally. Agreement between them is satisfactory and the transient response has been found to be described by a two-step activation model. The dependence of the latch-up trigger current on the duration time of the noise has been extensively studied in several cases of the double well structure to deduce design criteria for CMOS VLSI's with reasonable immunity against latch-up.