Design methodology of multiple-valued logic voltage-mode storage circuits

Abstract

A novel methodology designing for multiple-valued logic voltage-mode storage circuits is introduced. Using the proposed inverter-based unit, uni-signal controlled pass gates and True Single-Phase Clocked Logic-based output units, efficient r-ary (where r is the radix) dynamic and pseudo-static latches can be designed. They exhibit regular, modular, and iterative structure, which means that the for multiple-valued logic circuits are VLSI implementable. Also, these circuits use two kinds of MOS transistors, i.e., enhancement and depletion mode. Since we use only the clock signal, an additional contribution to low power dissipation of the derived circuits has been made. Comparisons with existing circuits prove substantial improvements in terms of speed, power consumption, and transistor count.