Design, Automation, and Test in Europe · 2004 · 47 citations · 10 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignSystem-on-chip DesignEnergy-efficient Embedded SystemsLow-power Digital Circuit DesignPower EstimationPower ManagementPower OptimizationPower-aware DesignBus EncodingCodingPower ConsumptionPower Consumption ModelingPower Consumption OptimizationPower-aware MicroarchitecturePower-efficient DesignSystem-on-chip Power Management
Encoding techniques which minimize the self- or coupling activity of buses are often proposed to reduce power dissipation on system buses. In this paper, we investigate the efficiency of several coding schemes for on-chip buses with respect to overall power dissipation. The power of the codec systems was estimated by power simulations with the lay-outs and related to the savings on the bus. We derived an expression for the energy efficiency of the codecs as a function of bus length (capacitive load). Despite the fact that adaptive schemes could obtain up to 40% savings, the bus lengths required to reduce the overall power consumption are not realistic for on-chip buses.
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R. Ho, Mark Horowitz · Proceedings of the IEEE · 2001 · 1.4K citations
Getting to the bottom of deep submicron
Dennis Sylvester, Kurt Keutzer · 1998 · 283 citations