Improved digital current control methods in switched reluctance motor drives

Abstract

This paper proposes a method to avoid current feedback filters in fast digital-based current loops in switched reluctance drives. Symmetrical pulsewidth modulation (PWM) and synchronized sampling of the phase current allow a noise-free current sampling with no antialiasing filter. This paper also proposes more efficient methods to chop the two transistors in the asymmetric inverter used with switched reluctance drives. A fast field-programmable gate array (FPGA)-based test system is used for validation of the new methods. Test results show a significant improvement in dynamic and steady-state current loop control compared with traditional methods. The new chopping method is found to reduce the switching losses and increase the drive efficiency.