2.6 kV 4H-SiC lateral DMOSFETs

Abstract

A 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4H-SiC substrate. After depleting through the epilayer, the depletion region continues to move laterally toward the drain. The result is an increase in blocking voltage compared to a vertical DMOSFET fabricated in the same epilayer on a conducting substrate. A blocking voltage of 2.6 kV is obtained, nearly double the highest previously demonstrated blocking voltage for a SiC MOSFET.