Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

TLDR

SOP technology using silicon carriers enables modular, high‑performance integration of heterogeneous chips and passive/active components, leveraging silicon through‑vias, high‑density wiring, and I/O interconnections to achieve SoC‑like performance with high yield and low cost. The paper investigates the technical challenges and recent progress in developing silicon carrier technology for new applications. The authors fabricate silicon carriers with existing manufacturing and mid‑UV lithography to create dense package wiring that follows CMOS back‑end‑of‑line rules, while matching the chip’s thermal expansion to preserve reliability as microbump interconnections shrink.

Abstract

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a "virtual chip" using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.