2008 · 10 citations · 16 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureFault-tolerant ComputingFault-tolerant SystemsEmbedded Memory BlocksHardware Fault ToleranceMemory DevicesMemory Subsystem DesignArea Overhead AnalysisCache MemoryEmbedded MemoryFault CoverageFault Coverage AnalysisMemory Circuit DesignMemory CircuitsOverhead Reduction
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities. On a 4 Mbit memory and an average number of 1024 memory defects per IC, a repair ratio of 100% and over 90% require less than 2% and 1% memory overhead respectively.
16
Built in self repair for embedded high density SRAM
Ilyoung Kim, Y. Zorian, G. Komoriya et al. · 2002 · 196 citations
Engineering, Computer Engineering, Electrical Engineering +17
Memory built-in self-repair using redundant words
V. Schober, Steffen Paul, O. Picot · 2002 · 95 citations