Detailed Simulation Study of a Reverse Embedded-SiGe Strained-Silicon MOSFET

Abstract

This paper presents an extensive simulation study of a MOSFET with reverse embedded-SiGe (Rev. e-SiGe), a new strained-silicon concept that utilizes elastic relaxation of a buried compressive SiGe layer to induce tensile strain in the channel. Simulations were executed to calculate the channel stress for device structures with a gate length between 32 and 10 nm, and including 4900 different combinations of the device parameters. The device parameters most critical for determining the channel stress are identified, and it is shown that optimization of the device structure to maximize the channel stress can be understood in a simple manner involving only two underlying variables, the t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SiGe</sub> /t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Si</sub> ; ratio and the silicon/SiGe island aspect ratio. A study of the practical limits to the critical determinants of channel stress is described, and the channel stress for optimized structures within these practical limits is simulated. The Rev. e-SiGe technique is shown to be effective, inducing a level of stress comparable to or exceeding conventional strained-silicon techniques, and it is shown to be scalable down to a gate length of 10 nm. An enhanced Rev. e-SiGe process is proposed involving spacer removal and gate recrystalization; simulations show that the enhanced process can nearly double the channel stress.