Thermal-Aware 3D Network-On-Chip (3D NoC) Designs: Routing Algorithms and Thermal Managements

Abstract

The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues in multicore systems by using die stacking technology in recent years. However, the high integration density of the stacking dies at high operating frequency results in large power density. Furthermore, the unequal thermal conductance of different logic layers leads the 3D NoC to face a much severer thermal problem than 2D NoC. Those thermal issues may limit the performance gain of 3D integration and cause lower reliability of the 3D NoC designs. To ensure the thermal safety, the 3D NoC systems generally require a better cooling method, which can be classified into "technological approaches" and "algorithmic/architectural approaches." The technological approaches work efficiently for removal of internal thermal hotspots through extra devices but results in drastically increasing fabrication cost. On the other hand, the algorithmic/architectural design approaches aim to use the approaches of intelligent packet data delivery and temperature control to maximize performance under thermal constraints. Compared with technological approaches, they can control the system temperature at much lower extra circuit/device cost. In this article, we focus on the algorithmic/architectural design approaches and review the modern packet routing algorithms and thermal managements for thermal-aware 3D NoC systems. Firstly, we introduce the thermal challenges of 3D NoC system and review the encountered design challenges. Then, recent developed techniques to handle the thermal challenges of 3D NoC systems are addressed.