3D Network-on-chip
A "3D Network-On-Chip" is a Network-On-Chip architecture that integrates multiple layers of interconnected processing elements in a three-dimensional stacked configuration to enhance communication efficiency and reduce interconnect delay compared to traditional planar designs.
159
Publications
5.1K
Citations
362
Authors
154
Institutions
Publications per year
2017–2026
37
Variants
3D Networks-on-chip3D Noc
Parents
159
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Igor Loi, Subhasish Mitra, Thomas H. Lee et al. · 2008 · 146 citations
Engineering, Computer Engineering, Electrical Engineering +17
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Igor Loi, Subhasish Mitra, Thomas H. Lee et al. · 2008 · 144 citations
Engineering, Computer Engineering, Electrical Engineering +17
Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems
Chih-Hao Chao, Kai-Yuan Jheng, Haoyu Wang et al. · 2010 · 134 citations
1–5 of 159
362
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154

National Taiwan University
Taipei, Taiwan
13 h-index
45 publications
2K citations

University of Turku
Turku, Finland
13 h-index
55 publications
1.7K citations

Washington State University
Pullman, United States
10 h-index
34 publications
943 citations

University of Aizu
Fukushima, Japan
9 h-index
22 publications
653 citations
Turku Centre for Computer Science
Turku, Finland
9 h-index
28 publications
815 citations
Duke University
Durham, United States
7 h-index
7 publications
174 citations

KTH Royal Institute of Technology
Stockholm, Sweden
6 h-index
14 publications
413 citations
University of California, Irvine
Irvine, United States
6 h-index
14 publications
377 citations
1–8 of 154
TPDS · 6 publications · 218 citations
6
h-index
6 publications · 234 citations
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5 publications · 276 citations
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MICPRO · 4 publications · 87 citations
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4 publications · 566 citations
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