3D Network-on-chip

A "3D Network-On-Chip" is a Network-On-Chip architecture that integrates multiple layers of interconnected processing elements in a three-dimensional stacked configuration to enhance communication efficiency and reduce interconnect delay compared to traditional planar designs.

159

Publications

5.1K

Citations

362

Authors

154

Institutions

Publications per year

2017–2026

37

Variants

3D Networks-on-chip3D Noc

Authors

362

  1. HT
    Hannu Tenhunen

    KTH Royal Institute of Technology, Sweden

    14 publications · 434 citations

    13

    h-index

  2. PL
    Pasi Liljeberg

    University of Turku, Finland

    12 publications · 362 citations

    12

    h-index

  3. AW
    An-Yeu Wu

    National Taiwan University, Taiwan

    11 publications · 496 citations

    11

    h-index

  4. PP
    Partha Pratim Pande

    Washington State University, United States

    10 publications · 296 citations

    10

    h-index

  5. AB
    Abderazek Ben Abdallah

    University of Aizu, Japan

    9 publications · 279 citations

    9

    h-index

1–5 of 362

Venues

  1. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 6 publications · 218 citations

    6

    h-index

  2. 6

    h-index

  3. IEEE Transactions on Computers

    5 publications · 276 citations

    5

    h-index

  4. Microprocessors and Microsystems

    MICPRO · 4 publications · 87 citations

    4

    h-index

  5. 4

    h-index

1–5