Novel Built-In Current-Sensor-Based $I_{\rm DDQ}$ Testing Scheme for CMOS Integrated Circuits

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents a new built-in current sensor (BICS)-based <formula formulatype="inline"><tex Notation="TeX">$I_{\rm DDQ}$</tex></formula> testing scheme for complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs). The proposed BICS will employ short detection times and low power dissipation to effectively ensure the reliability of the BICS and reduce the impact of the circuit under test (CUT) during testing. In addition, an <formula formulatype="inline"><tex Notation="TeX">$I_{\rm DDQ}$</tex></formula> testing scheme based on the proposed BICS for detecting the abnormal quiescent current is presented. A 16-kB CMOS static random access memory (SRAM) is used as the CUT in this paper to discuss the testing considerations, including fault models and the <formula formulatype="inline"><tex Notation="TeX">$I_{\rm DDQ}$</tex></formula> testing strategy. The simulation results show that the proposed BICS has a much improved performance compared with that in previous works. In addition, the physical chip design of the proposed BICS-based <formula formulatype="inline"><tex Notation="TeX">$I_{\rm DDQ}$</tex></formula> testing scheme for SRAM testing applications is also implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-<formula formulatype="inline"><tex Notation="TeX">$\mu \hbox{m}$</tex></formula> CMOS technology. The test results show that 100% fault coverage can be achieved with only a 1.23% area overhead penalty. </para>