IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2005 · 52 citations · 4 references
EngineeringComputer EngineeringComputer ScienceMicroelectronicsParallel AlgorithmsParallel ComputingCmos Circuit DesignDigital Integrated Circuit DesignMixed-signal Integrated Circuit DesignParallel ArchitecturesPipeline ParallelismTiming AnalysisHardware PipeliningLoop PipeliningMultiplexer DesignMultistage Pipeline DesignPipeline DesignPipelined CommunicationPipelined Digital Circuits
This paper presents novel approaches for pipelining of parallel nested multiplexer loops and decision feedback equalizers (DFEs) based on look-ahead techniques. Look-ahead techniques can be applied to pipeline a nested multiplexer loop in many possible ways. It is shown that not all the look-ahead approaches necessarily result in improved performance. A novel look-ahead approach is identified, which can guarantee improvement in performance either in the form of pipelining or parallelism. The proposed technique is demonstrated and applied to design multiplexer-loop-based DFEs with throughput in the range of 3.125-10 Gb/s.
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