Impact of ball via configurations on solder joint reliability in tape-based, chip-scale packages

Abstract

Three-dimensional finite element analysis has been applied to determine the time-dependent solder joint fatigue response of a tape based chip-scale package under accelerated temperature cycling conditions (-40C to +125C, 15min ramps/15min dwells). The effects of differing ball via configurations due to variations in both package assembly and tape vendors were investigated, including the use of punched, etched, laser etched, and enhanced re-flow pad area vias. The solder structures accommodate the bulk of the plastic strain that is generated during accelerated temperature cycling due to the thermal expansion mismatch between the various materials that encompass the chip-scale package. Since plastic strain is a dominant parameter that influences low-cycle fatigue, it was used as a basis for evaluation of solder joint structural integrity. An extensively published and correlated solder joint fatigue life prediction methodology was incorporated by which finite element simulation results were translated into estimated cycles to failure. This study discusses the analysis methodologies as implemented in the ANSYS finite element simulation software tool.