Failure Analysis of 1200-V/150-A SiC <sc>MOSFET</sc> Under Repetitive Pulsed Overcurrent Conditions

Abstract

SiC MOSFETs are a leading option for increasing the power density of power electronics; however, for these devices to supersede the Si insulated-gate bipolar transistor, their characteristics have to be further understood. Two SiC vertically oriented planar gate D-MOSFETs rated for 1200 V/150 A were repetitively subjected to pulsed overcurrent conditions to evaluate their failure mode due to this common source of electrical stress. This research supplements recent work that demonstrated the long term reliability of these same devices [1]. Using an RLC pulse-ring-down test bed, these devices hard-switched 600 A peak current pulses, corresponding to a current density of 1500 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Throughout testing, static characteristics of the devices such as B <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VDSS</sub> , R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS (on)</sub> , and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS(th)</sub> were measured with a high power device analyzer. The experimental results indicated that a conductive path was formed through the gate oxide; TCAD simulations revealed localized heating at the SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface as a result of the extreme high current density present in the device's JFET region. However, the high peak currents and repetition rates required to produce the conductive path through the gate oxide demonstrate the robustness of SiC MOSFETs under the pulsed overcurrent conditions common in power electronic applications.