Effects of voids on bump chip carrier (BCC++) solder joint reliability

Abstract

In this study, the effects of voids on the solder joint reliability of bump chip carrier (BCC++) packages on a printed circuit board are investigated. Emphasis is placed on the void size, void location, and void percentage. The solder is assumed to obey the Garofalo-Arrhenius creep constitutive equation. A total of 12 different cases are studied. In addition, the effects of voids on the crack growth in the BCC++ solder joint are studied by the fracture mechanics method. Emphasis is placed on the demonstration that a crack in the solder joint may be stopped by a void in front of it.