2005 · 49 citations · 13 references
EngineeringComputer EngineeringComputer ScienceFault ToleranceFault-tolerant ComputingFault-tolerant SystemsField-programmable Gate Array ArchitectureFpga ArchitectureHardware Fault ToleranceInterconnect ArchitectureRoutingRouting ArchitectureConnection Block DesignDetailed RoutingFault-tolerant Fpga ArchitectureFault-tolerant InterconnectsMultiplexersRedundancy SchemesRouting In Field-programmable Gate ArraysSignal Timing
Future process nodes’ shrinking feature sizes increase manufacturing defects, making defect tolerance critical for large FPGAs, and this work provides the first detailed analysis of fine‑grained defect‑tolerant routing schemes. The authors propose changes to island‑style FPGA routing architecture to tolerate multiple random interconnect defects without re‑routing and with minimal timing impact. Their scheme, a prebuilt user option, adds multiplexers (+11% area) and spare wiring tracks (24–34% overhead) to the architecture. The approach yields a programmable delay penalty of 5–10% at low defect rates (up to 25% when high), tolerates over ten defects in 128×128 arrays, and scales naturally with array size.
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate multiple defects (Campregher et al., 2005). We propose a number of changes to the detailed routing architecture of island-style FPGAs to tolerate multiple random, distributed interconnect defects without re-routing and with minimal impact on signal timing. Our scheme is a user option prebuilt into an architecture, requiring +11% area for additional multiplexers. Unused (spare) wiring tracks are also needed, bringing total overhead to 24% to tolerate stuck-at or open faults, or 34% to include bridging. User circuits that do not fully stress the routing network already have these tracks freely available. The delay penalty is programmable: 5-10% if defect rates are expected to be sufficiently low, but can be as high as 25% if defect rates are high. Our schemes can tolerate more than 10 interconnect defects for large array sizes of 128 /spl times/ 128. Unlike row/column redundancy schemes, our schemes are scalable: they naturally tolerate more defects as the FPGA array size increases. This work is the first detailed analysis of fine-grained defect-tolerant schemes in FPGAs.
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