ACM SIGPLAN Notices · 2001 · 26 citations · 11 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsSchedulingGraphics Processing UnitsInstruction SchedulingInstruction-level ParallelismMicroarchitecture DesignProcessor MicroarchitectureSuperscalar ProcessingEmbedded Processor DesignInstruction Scheduling AlgorithmsInteger Linear ProgrammingMultiply-accumulate UnitsOptimal Instruction SchedulingSimd ParallelismSuperscalar MicroarchitectureSuperscalar Scheduling
The IA‑64 architecture blends VLIW and superscalar principles and includes multiply/accumulate units and SIMD support for 3D graphics. This work proposes an integer‑linear‑programming formulation for instruction scheduling on IA‑64. The ILP model encodes data dependences, resource constraints, and bundling restrictions, treating these tightly coupled subproblems as a single optimization problem. A two‑phase solution strategy yields mostly optimal schedules within acceptable computation times.
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply/accumulate units and SIMD operations for 3D graphics operations. In this paper we present an ILP formulation for the problem of instruction scheduling for IA-64. In order to obtain a feasible schedule it is necessary to model the data dependences, resource constraints as well as additional encoding restrictions—the bundling mechanism. These different aspects represent subproblems that are closely coupled which gives the motivation for a modeling based on integer linear programming. The presented approach is divided in to two phases which allows us to compute mostly optimal solutions with acceptable computation time.
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James C. Dehnert, Ross A. Towle · The Journal of Supercomputing · 1993 · 202 citations
Itanium processor microarchitecture
H. Sharangpani, Harsh Arora · IEEE Micro · 2000 · 193 citations