XPRESS: a cell layout generator with integrated transistor folding

Abstract

We describe a method for generating area-efficient layouts of complex CMOS cells in the one-dimensional (linear) style. Its key features are the support for unrestricted circuit structures, transistor sizing via a novel folding technique that integrates folding into the synthesis algorithms, and optimal diffusion sharing. The method has been implemented in the XPRESS cell syntheses tool at the Intel Corporation, where it is in active use to lay out datapath cells for microprocessors.