A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs

Abstract

This paper presents a reconfigurable built-in self-repair (ReBISR) scheme for multiple repairable RAM cores with different sizes and redundancy organizations (i.e., spare rows/spare columns or spare rows/spare IOs). We also propose an efficient built-in redundancy-analysis (BIRA) algorithm for allocating redundancies for the ReBISR scheme. A reconfigurable BIRA (ReBIRA) circuit is realized to perform the proposed BIRA algorithm for the ReBISR scheme. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). The area cost of the reconfigurable BIRA is very small, e.g., the area cost is only about 1.5% if 512times4times256 design parameters and four memory instances (64times2times32, 128times2times64, 256times4times128, and 512times4times256) are considered. Also, the ratio of the redundancy analysis time to the test time is very small, e.g., the ratio for a 512times4times256-bit memory tested by a March-14N algorithm with solid data backgrounds is only about 0.25%