Effect of floating-body charge on SOI MOSFET design

Abstract

This work presents a new method for assessing the effect of floating-body charge on a fully- and partially-depleted Silicon-on-Insulator (SOI) MOSFET device design space. Floating-body effects under transient conditions are incorporated into the device design parameters threshold voltage V/sub T/ and off-current I/sub 0FF/ using calibrated two-dimensional (2-D) device simulation. Simulation methodology which reveals the worst-case bounds of the device design parameters, from idle to switching-steady-state, is presented and applied to a CMOS inverter example. Using this methodology, the worst-case shifts in V/sub T/ and I/sub 0FF/ due to hysteretic floating-body charge are quantified for devices in L/sub eff/=0.2- and 0.1-/spl mu/m design spaces. Methods to reduce floating-body effects are discussed including a demonstration of how reducing the effective bulk carrier lifetime widens the 0.1-/spl mu/m design space.