Circuit Simulation of Threshold-Voltage Degradation in a-Si:H TFTs Fabricated at 175

Abstract

This brief presents a novel approach to modeling gate bias-induced threshold-voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift with measured data in a TFT latch circuit.