Electrical modeling of Through Silicon and Package Vias

Abstract

This paper presents analytical modeling and 3D full-wave electromagnetic (EM) simulation of the bias voltage dependent semiconductor (MOS) capacitance of a Through Silicon Via (TSV). An accurate electrical model of the TSV is proposed by considering the semiconductor effects. The high-frequency electrical performance of TSVs and Through-Package Vias (TPVs) are compared by means of 3D EM simulations. A parametric study is performed on TSV capacitance and design guidelines are presented for signal and power TSVs.