IEEE Electron Device Letters · 2014 · 83 citations · 8 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsHigh-frequency Semiconductor DevicesMetal-oxide-semiconductor Field-effect TransistorsNanoelectronicsNanowiresSemiconductor PhysicsWide Band Gap SemiconductorsGate-all-around TransistorsNanowire DevicesNanowire Field-effect TransistorsNanowire TransistorsParasitic CapacitanceParasitic Capacitance ReductionSemiconductor NanowiresSmall-signal Modeling
We demonstrate a vertical InAs nanowire MOSFET integrated on Si substrate with an extrinsic peak cut-off frequency of 103 GHz and a maximum oscillation frequency of 155 GHz. The transistor has a transconductance of 730 mS/mm and is based on arrays of nanowires with gate-all-around and high-κ gate dielectric. Furthermore, small-signal modeling shows a ~80% reduction of the total parasitic gate capacitance when the metal pad overlap in the transistors is reduced through additional patterning.
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High-Performance InAs Nanowire MOSFETs
Anil W. Dey, Claes Thelander, Erik Lind et al. · IEEE Electron Device Letters · 2012 · 69 citations · Full text