An efficient and flexible architecture for high-density gate arrays

Abstract

The properties and performance of high-density gate arrays (HDGAs) are largely determined by the structure on which logic and memory functions are mapped. An architecture for an effective implementation of these functions is presented. All architecture in which each basic cell provides three nMOS and three pMOS transistors is given. Both nMOS and pMOS transistors share a common gate. The advantages of such an architecture can be fully exploited in memory and logic array structures like ROM, RAM, and PLA. Triple-metal BiCMOS processes are at present used to implement HDGAs. Replacing the expensive third metal layer with a TiSi/sub 2/ layer increases the silicon cost and processing time by no more than 5%. These straps are used to bridge only short distances, such as those within logic cells. They are also used for connecting transistors in parallel for increased driving capability. To show the benefits of the common-gate architecture, a 10*10-b fully pipelined multiplier was designed in custom standard cells using commercially available place-and-route software and then in an HDGA architecture.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>