A 240K transistor CMOS array with flexible allocation of memory and channels

Abstract

A CMOS masterslice containing about 240K transistors is described. A new basic cell was designed for efficient construction of both logic and memory cells. For flexible allocation of wiring channels, logic unit cells, and memory blocks, about 30000 basic cells with no dedicated channel regions are spread throughout the chip, except in the I/O region. Logic and memory blocks can be placed anywhere on the chip. A test chip, developed to investigate the feasibility of the masterslice design, reveals densities of 230 gates/mm/SUP 2/, 230 bit/mm/SUP 2/, and 1900 bit/mm/SUP 2/ for a 16/spl times/16-bit multiplier, a 1K SRAM, and a 4K ROM, respectively.