Electromigration reliability and current carrying capacity of various WLCSP interconnect structures

Abstract

Wafer Level Chip Scale Packages (WLCSPs) are increasingly being used in Power Management IC (PMIC) applications. Since these packages are typically of small size and low I/O count, the current per bump can be very high for these applications. Therefore, it is important to characterize the electromigration (EM) behavior of WLCSP interconnects to estimate their current carrying capacity. This paper provides an EM performance comparison of four (4) different WLCSP interconnects tested under the same condition. The configurations included: i) Ti/Cu/2.0 μm Ni UBM on 4μm Cu RDL, ii) Ti/Cu/8.6μm Cu UBM on 4μm Cu RDL, iii) Bump-on-trace with 9μm thick Cu RDL, and iv) Bump-on-trace with 14μm thick Cu RDL. A specially designed test vehicle with multiple EM test structures was used for this purpose. The packages were mounted on printed wiring boards (PWB) with either Cu/OSP or NiAu pad surface finish. These assemblies were then tested in a dedicated EM test system using 1.0Amp/161°C as the test condition. More than 4000 hours of testing have been completed so far. Clear differences between these WLCSP interconnects were observed in terms of EM performance. Samples were also removed at different times throughout the test so that detailed SEM analyses could be performed to understand and quantify the failure mode and progression of EM damage for each configuration. The EM performance is found to be significantly better for structures with a 2.0μm Ni UBM layer and the bump-on-trace structure with 14μm thick RDL with no failures so far. However, units with either 8.6μm thick Cu UBM structure or 9μm thick RDL bump-on-trace structure have resulted in a number of failures and at least 2X lower reliability compared to the other two structures. Further, PWB surface finish has a significant effect on EM performance with Cu/OSP performing better than NiAu finish.