The Influence of NBL Layout and LOCOS Space on Component ESD and System Level ESD for HV-LDMOS

Abstract

This paper investigates the influence of the N-type buried layer (NBL) layout and LOCOS space on the ESD performance and trigger voltage of the lateral DMOS (LDMOS) device. Without adequate LOCOS spacing, LDMOS is vulnerable to ESD damage. If the LOCOS space is sufficiently wide, adding NBL structure can further improve LDMOS ESD performance significantly. This is because NBL can switch the current passage from the surface channel region to the bulk NBL during an ESD zapping, thus, avoiding localized highly damaging ESD current flow in the channel region.