IEEE Journal of Solid-State Circuits · 1996 · 35 citations · 10 references
EngineeringElectrical EngineeringMicroelectronicsMicrowave EngineeringSemiconductor DevicesComplementary Metal-oxide-semiconductor TechnologyHigh-frequency Semiconductor DevicesIntegrated Circuit DesignMicrowave Integrated CircuitsMicrowave Semiconductor DevicesRadio-frequency Integrated CircuitsGaas Monolithic Microwave Integrated CircuitsInsertion LossIsolationMicrowave SwitchesMonolithic Microwave Integrated CircuitsParallel ResonanceParasitic CapacitanceRf Switches
In this paper, we propose two new types of dual-pole double-throw (DPDT) switch GaAs JFET monolithic microwave integrated circuits (MMICs) for digital cellular handsets. These ICs have the excellent characteristics of low insertion loss and high power handling capability, even with a low control voltage by stacking three JFETs with shallow V/sub p/ and using a novel bias circuit using p-n junction diodes. One DPDT switch IC has two shunt FET blocks and can achieve high isolation without external parts. An insertion loss less than 0.6 dB and isolation over 25 dB up to 2 GHz were achieved. P/sub 1dB/ was about 35 dBm even with a control voltage of 0/3 V. Another DPDT switch IC utilizes parallel resonance of external inductors and parasitic capacitance between the drain and the source of the OFF-state FETs. By attaching 15 nH inductors, for example, the IC exhibited an insertion loss as low as 0.4 dB, an isolation of better than 40 dB at 1.5 GHz, a bandwidth of about 400 MHz for 20 dB isolation, and P/sub 1dB/ of about 34 dBm with the 0/3 V control.
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Novel high performance SPDT power switches using multi-gate FET's
F. McGrath, C. Varmazis, C. Kermarrec et al. · 2002 · 36 citations
H. Uda, Takahiro Yamada, Terumitsu Sawai et al. · IEEE Journal of Solid-State Circuits · 1994 · 35 citations
SPDT switch MMIC using E/D-mode GaAs JFETs for personal communications
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