A half-micron SRAM cell using a double-gated self-aligned polysilicon PMOS thin film transistor (TFT) load

Abstract

An SRAM cell structure using stacked double-gated, self-aligned polysilicon PMOS thin-film transistors (TFT) is described. This memory cell has been realized in a half-micron, triple-poly, double-metal CMOS process; the cell area is 22.32 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , adequate for 4-Mb SRAMs. The main features are: (i) self-aligned structure to precisely define the TFT channel, (ii) TFT drive current enhancement by double gate effect, and (iii) the realization of sub-micron channel length TFTs, which demonstrates the feasibility of this cell for the next-generation 16-Mb SRAM