Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power

Abstract

Circuits based on magnetic logic have shown great promise as an extremely low power alternative to CMOS based circuits. However, the success or failure of such circuits hinges on the existence of a locally controllable and low power clock field. Existing work has largely assumed the availability of such a clock field that would be almost impossible to fabricate or that exhibits an ideal distribution in space. This paper uses a fabricatable clock structure proposed in as the basis to investigate all possible non-ideal properties (due to fabrication limitations and variations) of the resulting clock field. How such a clock impacts the logical correctness of a magnetic circuit element is verified via micromagnetic simulation. The impact on performance and power is also considered.