Planar GeOI TFET Performance Improvement With Back Biasing

Abstract

Reverse back biasing of a planar germanium-on-insulator tunneling field-effect transistor provides for significant improvement in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , by over an order of magnitude for 0.25 V operating voltage. Optimization of the gate-to-source overlap and source doping gradient is key to maximizing the benefit of back biasing.