A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing

Abstract

Combinations of circuit techniques enabling tolerance to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tau</sub> fluctuations in SRAM cell transistors during read or write operations and significant reductions in minimum operating voltage are reported. Implemented in a 9 Kb times 74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST, these techniques, demonstrate VMIN of 0.58 V and 0.40 V/0.54 V for single and dual V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> implementations respectively. The techniques consume a 10-12% overhead in area, improve performance marginally and also enable over 50% reduction in cell leakage with minimal circuit overhead.