Electrical performance of bumpless build-up layer packaging

Abstract

The bumpless build-up layer (BBUL) microelectronic packaging technology is characterized by the absence of a conventional substrate core and a direct extension of the outmost metallization layers of the die into the overall thin substrate. Such a coreless, thin package provides the advantages of small electrical loop inductance for power delivery and minimized discontinuities for high-speed signaling. Furthermore, it allows for reduced thermomechanical stresses on low dielectric constant (low-k) die materials, high lead count, and ready integration of multiple electronic, optical, and microelectromechanical components. BBUL is also expected to be compatible with innovative thermal solutions using frontside heat removal. After summarizing some of the non-electrical characteristics of the BBUL packaging technology we conduct transient electromagnetic (EM) simulations for the core power delivery problem.