2002 · 36 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ScalingIntegrated Circuit DesignLow-power Digital Circuit DesignNanoelectronicsCmos Logic CircuitsCurrentsLogic Gate DelayLow-voltage Cmos DesignSiliconUltra-low-power Cmos
The authors describe the initial implementation of MOSAIC V (Motorola oxide isolated self-aligned implanted circuits, fifth generation), a novel silicon process technology. A number of innovative process approaches and novel methods of aggressive device scaling result in deep submicron device structures in the range of 0.1-0.4 mu m. A very low speed-power product of 92 fJ at 3.3-V supply voltage for ECL (emitter coupled logic) gates is obtained in the lower range of operating currents, with typical gate delays of 73 ps at 100 mu A and 35 ps at 800 mu A switch currents. Using a selectively implanted collector, a minimum ECL gate delay of 29 ps at 800 mu A switch current is achievable.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
3
High-performance subquarter-micrometer gate CMOS technology
Y. Okazaki, Takashi Kobayashi, M. Miyake et al. · IEEE Electron Device Letters · 1990 · 18 citations