A 1-10Gbps PAM2, PAM4, PAM2 Partial Response Receiver Analog Front End with Dynamic Sampler Swapping Capability for Backplane Serial Communications

Abstract

A 1-10 Gbps receiver analog front end in 0.13 /spl mu/m CMOS enables a SERDES cell for backplane serial communications using differential PAM2, PAM4, or PAM2 partial response signaling with adaptive equalization. Dynamic sampler swapping and various built-in diagnostic capabilities enable receiver calibration and self-characterization with accuracy of < 0.4% UI in timing and < 2mV in voltage while receiving live data. Self-characterization results motivate modifications enabling communications at a BER of 10/sup -15/ with receiver sensitivity of +/-15mV.