A Multiplication-Accumulation Computation Unit with Optimized Compressors and Minimized Switching Activities

Abstract

A low-power multiplication-accumulation computation (MAC) unit using the radix-4 Booth algorithm is proposed; its architectural complexity is reduced and switching activities are minimized. However, to maintain a high performance, the critical delays and hardware complexities of MAC units are explored to derive a MAC unit with high performance and low hardware complexity. A carry-save addition operation with optimized compressors is proposed to omit the use of half adders to reduce the hardware complexity further. A scheme to reduce switching activity is also proposed to lower the power consumption of the MAC unit. In performing a MAC for X/spl times/Y+Z, the effective dynamic ranges of X and Y are detected; the one with the smaller effective dynamic range is processed for Booth decoding so as to increase the probability of the partial products being zero, and thus the switching activity is reduced. Also, the effective dynamic range of the result from this multiplication is estimated and compared with the effective dynamic range of the datum, Z. The larger effective dynamic range of the two data is considered as the effective word length for an addition operation. Pipelined latches are used to make the noneffective operation maintain the status of the previous operation so as to reduce the switching activities from the addition performed in MAC. After the addition operation, sign extension is performed on the result from the effective sign bit copied to non-effective bits to derive at a correct output datum. Compared to conventional MAC units, the proposed one is able to reduce 21.09% to 43.74% of power consumption. Additionally, the proposed MAC unit outperforms conventional ones in comparing the product of critical delay, area, and power consumption.