IEEE Design & Test of Computers · 2003 · 16 citations · 2 references
EngineeringComputer EngineeringManufacturing EngineeringComputer ArchitectureComputer-integrated ManufacturingDesign AutomationBuilt-in Self-testDesign For TestabilityEmbedded DebuggingEmbedded Reconfigurable SystemsHardware DebuggingReconfigurable System ArchitectureBuilt-in Test ArchitectureEmbedded TestabilityInfrastructure TestingManufacturingSystem-on-chip Reconfiguration
Embedding infrastructure IP to optimize chip-level manufacturing test and debugging has recently become common practice. However, adopting the same approach for boards and systems requires a different family of infrastructure IP. This article introduces such a family and discusses how it can optimize manufacturing test and debugging, as well as support configurability, especially in today's reconfigurable products.
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Hierarchical boundary-scan: a Scan Chip-Set solution
Steven M. Harrison, G. Noeninckx, P. Horwood et al. · 2002 · 10 citations
Engineering, Computer Engineering, Electrical Engineering +16