Comparisons of Design and Yield for Large-Area 10-kV 4H-SiC DMOSFETs

Abstract

Three large-area 10-kV 4H-SiC DMOSFET designs are compared with respect to their design, die area, breakdown yield, and ON-state yield. The largest of these DMOSFETs had 0.62 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of active area on a 1-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die, with a 10-kV device producing 40 A at a gate field of 3 MV/cm. Two designs used linear interdigitated fingers, whereas the third design used a square cell layout. The linear interdigitated finger design proved to be more robust, with higher yields than the square cell geometry. It was determined that the square cell design was yield limited due to the impact of wafer bow and total thickness variations on photolithographic accuracy, making the square cell geometry less attractive for large-area 4H-SiC DMOSFETs.