Thermal budget limits of quarter-micrometer foundry CMOS for post-processing MEMS devices

Abstract

Thermal budget limits for low stand-by power ( LSP), 0.25 /spl mu/m foundry CMOS devices have been investigated, in order to assess the impact of post-processing microelectromechanical devices devices. Resistance increases for vias (metal-to-metal contacts) rather than transistor-performance shifts limits the post-processing thermal budget. An empirical relation is found to predict the via resistance increase for various annealing conditions, based on third-order reactions of vacancies supplied by surface diffusion of metal atoms. The resistance increase is strongly dependent on annealing time and temperature. With a criterion of 10% increase, 6 h at 425/spl deg/C, 1 h at 450/spl deg/C, and 0.5 h at 475/spl deg/C are the maximum allowable thermal budgets, respectively. Electromigration (EM) of via chain structures was also evaluated, and after annealing for 6h at 425/spl deg/C showed only a 33% decrease in the EM lifetime.