2010 · 21 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringComputer NetworksMicroelectronicsVlsi DesignCmos Circuit DesignInterconnect ArchitectureInterconnect DesignNetwork-on-chip DesignRoutingRouting ArchitectureBandwidthBisection BandwidthNetwork Capacity UtilizationNetwork Resource UtilizationNetwork-on-chipNetwork-on-chip ArchitecturesVirtual ChannelsVlsi Implementation
A packet-switched 6×4 2D mesh network-on-chip (NoC) on a dedicated voltage and frequency island (VFI) provides 2 Tb/s of bisection bandwidth, and interconnects 48 Pentium <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">™</sup> class IA-32 cores and 4 DDR3 channels. The 1.28 Tb/s router with 16 B, 5.4 mm links achieves high network utilization through 8 virtual channels (VC), early-buffer write and read, route pre-computation and a 1-cycle wrapped wavefront allocator (WWFA) design. The 640 K transistor, 1.17 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> router operates at 2 GHz at 1.1 V while dissipating 550 mW. Router energy efficiency scales up to 7.2 Tb/s/W.
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William J. Dally · IEEE Transactions on Parallel and Distributed Systems · 1992 · 1.2K citations
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
Jason Howard, Saurabh Dighe, Yatin Hoskote et al. · 2010 · 598 citations