IEEE Transactions on Nuclear Science · 2002 · 48 citations · 15 references
EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyCurrent-voltage CharacteristicsHeavy-ion PhysicsIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsBipolar Junction Transistor ModelingBipolar Junction Transistor SimulationCurrent GainHeavy-ion ReactionsMetal-oxide-semiconductor Field-effect Transistor ModelingRadiation EffectsSingle Event EffectsSingle Event Upset Modeling
The parasitic bipolar transistor of NMOS/SOI transistors is a key element to determine the single-event upset (SEU) sensitivity. Parasitic bipolar transistor response has been investigated through transient current measurements induced by high energy heavy ions and three-dimensional (3-D) simulations. Experimental results reported allow to estimate the parasitic current gain as a function of the heavy ion location in the MOS transistor.
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A 50 nm depleted-substrate CMOS transistor (DST)
R. Chau, J. Kavalieros, Barry M. Doyle et al. · 2002 · 101 citations
Single-event charge enhancement in SOI devices
L. W. Massengill, E.V. Kerns, S.E. Kerns et al. · IEEE Electron Device Letters · 1990 · 92 citations
Engineering, Computer Engineering, Electrical Engineering +13
Model for CMOS/SOI single-event vulnerability
S.E. Kerns, L. W. Massengill, D.V. Kerns et al. · IEEE Transactions on Nuclear Science · 1989 · 65 citations
Engineering, Computer Engineering, Electrical Engineering +17