Digital architecture of the new ATLAS pixel chip FE-I4

Abstract

With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is made of 80×336 pixels and features a reduced pixel size of 50×250 ¿m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire pixel array and the pixels organized in regions. In this paper, the digital architecture of FE-I4 is presented as well as the complete data flow.