Publication | Closed Access
Electrical properties and detection methods for CMOS IC defects
140
Citations
34
References
2003
Year
Unknown Venue
EngineeringCmos Failure ModesIntegrated CircuitsHardware SystemsReliability EngineeringCircuit SystemNanoelectronicsFailure AnalysisInstrumentationElectrical EngineeringCmos Ic DefectsComputer EngineeringBuilt-in Self-testMicroelectronicsDesign For TestingSilicon DebuggingTest VectorCircuit ReliabilityFault Injection
CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and I/sub DDQ/ test strategies, no single method guarantees detection of all types of CMOS defects. The I/sub DDQ/ test is the most sensitive and comprehensive, but can miss certain open-circuit defects and is a relatively slow measurement technique. The test-vector approach detects fewer of the CMOS defects, but can run at fast clock rates to detect certain open-circuit faults that may not be detectable by the I/sub DDQ/ test. Maximal CMOS IC defect detection involves a mixed-mode strategy of I/sub DDQ/ tests and vector stimulus/response tests.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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