170V Super Junction - LDMOST in a 0.5 μm commercial CMOS/SOS technology

Abstract

This paper reports on an experimental 170V Super Junction - LDMOST (SJ-LDMOST) implemented in a 0.5 /spl mu/m CMOS/SOS technology developed primarily for low voltage RF and mixed signal applications. An experimental SJ-LDMOST with a drift region length of 10 /spl mu/m and a drift region pillar doping concentration of /spl sim/2x10/sup 17/cm/sup -3/ exhibits a breakdown voltage of 170 V. The high average lateral electric field of 17V//spl mu/m implies that (near) charge compensation, between the alternating polarity pillars, has been achieved. 3D device simulations predict that the silicon limit in conventional LDMOSTs can be broken when the aspect ratio of pillar height to width exceeds 1.2 /spl mu/m/0.3 /spl mu/m.