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Device Design of High–Speed Source–Heterojunction–MOS Transistors (SHOTs): Optimization of Source Band Offset and Graded Heterojunction
16
Citations
5
References
2007
Year
Device SimulatorSource Band OffsetElectrical EngineeringSemiconductor TechnologyEngineeringHigh-speed ElectronicsWide-bandgap SemiconductorSemiconductor DeviceElectronic EngineeringApplied PhysicsDevice DesignGraded HeterojunctionQuantum EngineeringDrain Bias
We have studied the device design of 15-nm highspeed n-channel source-heterojunction-MOS transistors (SHOTs) utilizing high-velocity electron injection from the source into the channel region and using the conduction-band-offset energy between the source and the channel regions. The band-offset energy near the source region and the length of the graded heterojunction are key parameters for realizing high-speed operation of SHOTs. A 2D device simulator indicates that the enhancement in transconductance G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> in SHOTs on an SOI substrate over conventional SOI-MOSFETs without source-heterojunction structures strongly depends on the source conduction-band-offset value DeltaE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> and the length of graded-heterojunction structures L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> in SHOTs. Moreover, the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> enhancement of SHOTs is affected by the drain and the gate biases. We have shown that, with fully optimized DeltaE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> values, the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> enhancement of SHOT due to high-velocity electron injection can be achieved in a whole range of drain bias. The optimized SHOT is quite promising for high-speed CMOS devices in the 10-nm regime.
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