Core architecture optimization for heterogeneous chip multiprocessors

TLDR

Previous studies have shown single‑ISA heterogeneous multi‑core architectures improve power and performance, but none have addressed how to design such processors from scratch. The study investigates which core characteristics yield the highest area or power efficiency when designing a heterogeneous multi‑processor from scratch. The authors evaluate core designs across varying thread‑level parallelism levels and multiple area and power budgets. The study finds that heterogeneous chip multiprocessors, with cores customized to distinct application subsets, achieve up to 40 % performance gains, though customization incurs additional cost, and that core performance ordering differs across applications.

Abstract

Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores. This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous multi-processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets. The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characteristics — no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cores in terms of resources and complexity. This methodology produces performance gains as high as 40%. The performance improvements come with the added cost of customization.